As we reach the end of 2025, we’d like to take the opportunity to reflect on all of Universal Chiplet Interconnect Express™ (UCIe™) Consortium’s accomplishments throughout this year. It’s been a year defined by accelerating momentum, deeper industry collaboration, and meaningful progress across the chiplet ecosystem. Let’s review some of our favorite 2025 highlights as we approach the end of another busy year of chiplet innovation: 1.      We released the UCIe 3.0 Specificati

In a recent webinar , we had an amazing panel of Universal Chiplet Interconnect Express™ (UCIe™) member companies - Archana Cheruliyil from Alphawave Semi, Justin Bunnell from Siemens EDA, Manuel Mota from Synopsys, Mayank Bhatnagar from Cadence, and Vishal Chandrasekar from Ayar Labs - moderated by Brian Rea, UCIe Marketing Chair. Together, they explored how UCIe is accelerating the era of chiplet-based design through real-world collaboration, flexibility, and innovation. 

The Universal Chiplet Interconnect Express™ (UCIe™) Consortium is happy to be a part of this year’s Supercomputing 2025  event in St. Louis, Missouri from November 16-21, 2025! Be sure to stop by the Open Standards Pavilion in Booth #211  to learn more about   the UCIe 3.0 specification , which delivers significant performance gains with support for 48 GT/s and 64 GT/s data rates, along with architectural enhancements that improve bandwidth density, power efficiency, and syst

Authors: Mayank Bhatnagar (Cadence), Manuel Mota (Synopsys) and Dana Neustadter (Synopsys)   In part one of this blog, we examined how...