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Why Electrical Design Matters in Chiplet Architectures – Part Two: UCIe Latency and Security
Authors: Mayank Bhatnagar (Cadence), Manuel Mota (Synopsys) and Dana Neustadter (Synopsys) Â In part one of this blog, we examined how...
UCIe Marketing
Sep 296 min read
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UCIe 3.0 Specification: Redefining Chiplet Interconnects
The semiconductor industry is undergoing a seismic shift. Traditional monolithic chip designs cannot keep pace with skyrocketing demands...
UCIe Marketing
Sep 32 min read
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Why Electrical Design Matters in Chiplet Architectures – Part One: Signal Integrity and Power Delivery
Authors: Mayank Bhatnagar (Cadence), Soheil Modirzadeh (Synopsys) and Sajani Patel (Synopsys) As the semiconductor industry accelerates...
UCIe Marketing
Aug 294 min read
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UCIe at the Future of Memory and Storage 2025
The UCIe Consortium had a dynamic presence at this year’s Future of Memory and Storage (FMS) event , engaging attendees through important...
UCIe Marketing
Aug 264 min read
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