UCIe™ in Optical Networking

The semiconductor industry is experiencing new opportunities as a result of the industry’s rapid advancement of AI, creating a growing demand for effective and interoperable chiplet solutions. Just ahead of the Optical Fiber Communication Conference and Exhibition (OFC) 2025 conference, Universal Chiplet Interconnect Express™ (UCIe™) Consortium members Terry Thorn, VP Commercial Operations, Ayar Labs, Brig Asay, Senior Director of Network and Datacenter Solutions, Keysight Technologies, and Letizia Giuliano, Vice President Product Marketing and Management, Alphawave Semi, discussed the advantages of UCIe technology, use of chiplet technology in optical networking and data center interconnects, and more.

What advantages does using UCIe provide beyond interoperability?

Terry Thorn, Ayar Labs: As the semiconductor industry increases the use of chiplets, UCIe is vital to ensure we have a consistent die-to-die interconnect standard. This standards-based approach enables pre-silicon interoperability test suites as well as ensuring the efforts of engineering resources scale to the broader market as they focus design efforts on broad industry adoption versus custom efforts. 

Brig Asay, Keysight: With the increasing number of AI and other compute-intensive workloads, there is an equivalent need for energy efficiency while not sacrificing performance. UCIe is well-suited for high Tbps/mm performance while target sub-pJ/bit efficiency. UCIe has introduced a 3D integration specification which will drive efficiency even higher. Whether it’s extending battery life for mobile devices or reducing data center power consumption, the semiconductor industry must adopt more measures to improve efficiency, and UCIe is well positioned to address those needs.

Scalability, perhaps one of the most important advantages, accommodates different process nodes, architectures, use cases and performance metrics. In fact, functions within a chip scale differently and are optimized for certain process nodes. Digital logic favors smaller node sizes for power savings and dense integration. In contrast, analog blocks often do not benefit from migrating to the latest node size. This mixed architecture can be implemented faster with standards like UCIe as there are flexible package types that offer flexibility for the designer. This flexibility extends to incorporating 3rd party IP from an open ecosystem where turnkey solutions can accelerate time to market if both parties follow the same UCIe standard.

How do you see UCIe meeting the future demands of optical networking and data center interconnect?

Terry Thorn, Ayar Labs: Large-scale AI is driving the need to connect hundreds and thousands of compute chips across racks of servers in a data center. Ayar Labs TeraPHY™ optical chiplets built with UCIe-compliant electrical interfaces can be used for extended distances between packages and will act as protocol-agnostic retimers that use optical technology to eliminate distance barriers while using UCIe as the PHY layer between chiplets.

Brig Asay, Keysight: One of the challenges for data centers is high compute density and aggregate bandwidth requirements. UCIe and other die-to-die interconnects, along with the continual scaling of device integration, has enabled a significant growth in device performance. However, this die-to-die communication is only within a single device package. Chip-to-chip, chip to module and rack-to-rack communications have not scaled latency and bandwidth as much as chiplet technologies have. Recent product announcements of co-packaged optics (CPO) and other Silicon Photonics (SiPh) based solutions are paving the way for eventual broader adoption of both electrical and optical UCIe links. This disaggregation of compute has necessitated an equal intra- and inter-chip interconnect performance.

Letizia Giuliano, Alphawave Semi: UCIe provides an extremely energy-efficient interface for offloading compute, memory, etc., to I/O, which can be coupled with silicon photonics or other optoelectronic devices to extend the reach of the end point. When we look towards 448G SerDes I/O to enable next generation AI architectures, we don’t know what that architecture could be, but by using UCIe on the compute or high radix switch, one could easily swap between an electrical co-packaged copper I/O solution for short reaches or a co-packaged optics I/O chiplet for longer reaches like a scale out network.

How is UCIe supporting your efforts to scale optical I/O solutions?

Letizia Giuliano, Alphawave Semi: Copper-based electrical connections have inherent distance limitations when linking chips. UCIe compliance enables the PHY to be optimized as a retimer for optical applications. By leveraging pluggable optics, connectivity can extend to hundreds of meters without the signal loss typical of copper interconnects. This approach supports high-bandwidth, low-latency, and energy-efficient optical data transmission along the same physical shoreline.

Visit the UCIe Consortium kiosk in the Ayar Labs booth (Booth No. 2958) at the 2025 Optical Fiber Communications Conference and Exhibition from March 30 – April 3, 2025, where we will be highlighting unique UCIe Consortium member solutions to learn more about UCIe applications in optical communications and networking.