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Electronic Circuit Board

Specifications

Universal Chiplet Interconnect Express™

 

The UCIe™ Specifications are an open industry standard developed to establish a ubiquitous interconnect at the package level and covers the die-to-die I/O physical layer, Die-to-Die protocols, and software stack which leverage the well-established PCI Express® (PCIe®) and Compute Express Link™ (CXL™) industry standards. The specifications are available by request below.

UCIe 1.0 Specification 

​The UCIe specification details the complete standardized Die-to-Die interconnect with physical layer, protocol stack, software model, and compliance testing that will enable end users to easily mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) construction, including customized SoC.  â€‹

In-Standard & Advanced Package Benefits

  • Enables construction of SoCs that exceed maximum reticle size

  • Reduces time-to-solution 

  • Lowers portfolio cost (product & project)

  • Enables a customizable, standard-based product for specific use cases 

  • Scales innovation (manufacturing and process locked IPs) 

UCIe 1.1 Specification 

The UCIe 1.1 Specification delivers valuable improvements in the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. Additional enhancements are included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. The specification also details architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The UCIe 1.1 Specification is fully backward compatible with the UCIe 1.0 Specification.

Highlights of the UCIe 1.1 Specification:

  • Architectural Specification Enhancements enable compliance testing

  • Supports simultaneous multiprotocol with full link layer functionality for streaming protocols   

  • Includes runtime health monitoring and repair for automotive and high-reliability applications

  • New bump maps result in lower cost packaging

UCIe 2.0 Specification 

The UCIe 2.0 Specification adds support for a standardized system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets – from sort to management in the field. The introduction of optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions, allows vendor agnostic chiplet interoperability across a flexible and a unified approach to SIP management and DFx operations.


Additionally, the 2.0 Specification supports 3D packaging – offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. UCIe-3D is optimized for hybrid bonding with a bump pitch functional for bump pitches as big as 10-25 microns to as small as 1 micron or less to provide flexibility and scalability.

Highlights of the UCIe 2.0 Specification:

  • Holistic support for manageability, debug, and testing for any System-in-Package (SiP) construction with multiple chiplets.

  • Support for 3D packaging to significantly enhance bandwidth density and power efficiency.

  • Improved system-level solutions with manageability defined as part of the chiplet stack.

  • Optimized package designs for interoperability and compliance testing.

  • Fully backward compatible with UCIe 1.1 and UCIe 1.0.

UCIe 3.0 Specification 

The UCIe 3.0 specification marks the next stage in the evolution of open chiplet standards. The specification delivers significant performance enhancements, most notably support for 48 GT/s and 64 GT/s data rates, alongside architectural updates to meet growing industry demand for high-speed, interoperable chiplet solutions. These advancements improve bandwidth density, power efficiency, and system-level manageability, key enablers for scalable multi-chip System-in-Package (SiP) designs to accelerate innovation in modular semiconductor design.​

Highlights of the UCIe 3.0 Specification:

  • Support for 48 GT/s and 64 GT/s data rates, doubling the bandwidth of UCIe 2.0 (32 GT/s) to meet high-performance chiplet demands

  • Extended sideband channel reaching up to 100mm supports more flexible SiP topologies

  • Support for continuous transmission protocols through mappings, enabling uninterrupted data flow in Raw Mode for new applications such as connectivity between SoC and DSP chiplets

  • Early firmware download standardization using Management Transport Protocol (MTP) for streamlined initialization

  • Priority sideband packets allow deterministic, low-latency signaling for time-sensitive system events

  • Fast throttle and emergency shutdown mechanisms provide immediate system-wide notifications

  • Open Drain Pins to enable low-latency, bi-directional events

  • Power saving via runtime recalibration and L2 optimization enables power-efficient link tuning during operation

  • Fully backward compatible with all previous UCIe specifications for seamless integration and adoption

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