Chiplet Summit 2026: UCIe Momentum Across a Growing Ecosystem

Chiplet Summit 2026 underscored the accelerating momentum behind the chiplet movement and the central role UCIe is playing in shaping it. With strong representation from member companies across keynotes, technical sessions, tutorials, and live demonstrations, the event highlighted how quickly UCIe has evolved from specification to implementation. The breadth of participation - from Arm, Marvell, Cadence, Synopsys, Siemens, and Eliyan in sponsored presentations, to a vibrant exhibit floor featuring Alphawave Semi, Cadence, Siemens, Synopsys, Keysight Technologies, Tenstorrent, Menta, VeriSilicon, proteanTecs, InPsytech, Extoll, and others - demonstrated that UCIe is rapidly becoming the de facto standard for open die-to-die connectivity.

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A Strong Presence for the UCIe Consortium

The UCIe Consortium was proud to sponsor the “Applying Die-to-Die Interfaces” tutorial session, organized and moderated by Brian Rea, UCIe Consortium Marketing Working Group Chair. Industry leaders from Intel and Google provided practical guidance on UCIe fundamentals, protocol and logical layer design considerations, interoperability, manageability, and security. The session emphasized real-world lessons learned as companies deploy UCIe across optical chiplets, composable SoCs, and advanced multi-die architectures. The message was clear: UCIe is enabling teams to move from specification to silicon with confidence.

On the show floor, Intel and Cadence showcased the industry’s first live UCIe-S interoperability demonstration using the “Cameron Creek” test chip. By connecting independently designed Intel and Cadence chiplets implementing 16G UCIe-S PHY IP, the demo validated true cross-vendor interoperability and successful UCIe Interoperability Testing. Additional UCIe demonstrations at the Intel and Alphawave Semi kiosks in the UCIe booth reinforced that silicon is no longer theoretical, it is operational.

Keynote: Enabling an Open Chiplet Ecosystem

In a well-received keynote, Debendra Das Sharma, Chair of the UCIe Consortium, framed the industry’s transition from monolithic SoCs to system-in-package architectures as a structural shift that positions chiplets as the primary driver of scalable innovation. He walked through the evolution of UCIe from the foundational planar interconnect of UCIe 1.0, to vertical scaling with UCIe-3D in 2.0, and now to UCIe 3.0, which doubles planar bandwidth density and introduces runtime power and manageability enhancements for AI and HPC systems.

Importantly, Debendra emphasized the Consortium’s commitment to establishing UCIe as a multi-decade industry standard, one designed for longevity, broad interoperability, and ecosystem-wide innovation. The keynote reinforced that UCIe is not just solving today’s challenges but laying the groundwork for the next generation of heterogeneous computing.

UCIe Consortium Wins Best in Show for Connectivity & Interoperability

The UCIe 3.0 Specification was honored with the Chiplet Summit Best in Show Award for Connectivity & Interoperability. This recognition reflects the industry’s acknowledgement of UCIe 3.0 as a major milestone in open die-to-die standards. The latest specification doubles data rates to 48 GT/s and 64 GT/s, supports continuous transmission protocols, strengthens power optimization, and enhances manageability for scalable deployments.

“The UCIe Consortium represents a broad range of leading technology companies that see the importance of expanding the chiplet ecosystem,” said Chuck Sobey, General Chair, Chiplet Summit. “The 3.0 specification increases die-to-die data rates, power efficiency, and system-level manageability – all critical to scaling interoperable, multi-vendor chiplet architectures. We congratulate UCIe Consortium on this well-deserved recognition.”

By raising the bar on bandwidth density, efficiency, and system-level coordination, UCIe 3.0 sets a new benchmark for reliable, scalable chiplet integration. The award underscores its importance as a foundational technology for next-generation high-performance system-in-package (SiP) designs, helping the ecosystem meet the accelerating demands of AI, HPC, and heterogeneous computing.

UCIe Momentum Is Converting Into Industry Standardization

Across keynotes, tutorials, technical sessions, and live interoperability demos, the message from Chiplet Summit 2026 was clear: UCIe adoption is not only expanding but also maturing. What began as an ambitious effort to standardize die-to-die connectivity is now visible in production silicon, cross-vendor demonstrations, and award-winning specifications. The ecosystem is growing in depth and diversity, with strong participation from semiconductor leaders, IP Providers, EDA companies, and system innovators.

While technical challenges remain and continued industry collaboration is critical, the trajectory is unmistakable. UCIe is rapidly solidifying its position as the open, interoperable foundation for chiplet-based system design, poised to support scalable, heterogeneous computing innovation into the next decade and beyond.