Meet UCIe Consortium Member: GUC

UCIe Consortium member GUC recently shared details on its contribution to the development of the UCIe® (Universal Chiplet Interconnect Express®) specification, the company’s UCIe roadmap, and the benefits of becoming a Consortium member.

Can you share a brief introduction of GUC?

GLOBAL UNICHIP CORP. (GUC) is a market leader in advanced ASIC (application-specific integrated circuit) services. GUC’s comprehensive design services include ‘spec-in’ and SoC (System-on-Chip) integration, physical implementation, advanced packaging technologies, turnkey manufacturing and cutting-edge IPs such as HBM, UCIe, and GLink-3D for die-on-die stacking.

GUC leads the ASIC service market in the AI (Artificial Intelligence), HPC (High-Performance Computing), Networking, SSD (Solid-State Drive), industrial and several other segments. GUC is committed to expertly delivering to customers the most competitive PPA (power, performance, and area) designs, promising quality and yield. GUC also dedicates itself to differentiating the company’s ASIC products in the highly competitive market through engineering excellence.

TSMC is GUC’s sole foundry supplier and its closest partner in advanced process and packaging technologies. Leveraging this deep-rooted relationship, GUC can conquer various design and manufacturing challenges to deliver excellence in everything we produce.

What prompted GUC to join the UCIe Consortium?

Before joining the UCIe Consortium, GUC spent years developing Die-to-Die (2.5D) and Die-on-Die (3D) IPs for advanced packaging, which was successfully marketed as GLink (GUC die-to-die Link). While many AI, HPC, and Networking customers adopted GLink, an increasing number of clients began requesting compatibility with chiplets from multiple vendors to accelerate their time-to-market.

This trend highlighted the urgent need for an industry standard to facilitate a robust ecosystem for AI, HPC, and Networking customers. Believing that our years of GLink experience could benefit the broader industry, GUC joined the UCIe Consortium in 2022 to collaborate with partners in building this ecosystem.

What is the importance of a chiplet ecosystem to GUC?

For AI, HPC, and Networking applications, multi-die integration using 2.5D and 3D packaging is a "mega-trend" driven by the demand for higher transistor density and maximized performance. A chiplet-based approach offers "Lego-like" flexibility, allowing for better system partitioning and reuse. Furthermore, customers can optimize costs by manufacturing each chiplet at the most cost-effective technology node. A unified, prosperous chiplet ecosystem is essential for GUC to deliver complete, cost-effective solutions to our customers.

How does GUC contribute/plan to contribute to the Consortium?

As a Contributor member, GUC actively participates in various UCIe working groups and provides feedback based on our extensive 2.5D/3D packaging experience. We have collaborated with a major European automotive vendor to propose automotive-specific features for the UCIe specification. With the recent announcement of UCIe-3D in the 3.0 specification, we plan to contribute further hands-on experience in 3D stacking.

Can you share some UCIe technology use cases that GUC is bringing/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?

The AI, HPC and Networking sectors are GUC’s main focus. By leveraging UCIe-A and UCIe-3D interconnects, we enable the integration of massively increased transistor densities through 2.5D and 3D packaging. This chiplet-based approach allows GUC to combine specialized silicon from various process nodes, delivering superior yields, higher design flexibility and faster time-to-market. We are currently collaborating with tier-one Cloud Service Providers (CSPs) to deploy these next-generation UCIe implementations in hyperscale data centers.

Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?

We are excited to share that GUC’s UCIe-A portfolio now spans from 24G to 64G speeds, fully supporting TSMC’s advanced 5nm through 2nm technologies. Our roadmap includes innovative “face-up” IP designed for vertical 3D IC stacking, providing our clients with maximum flexibility across all chiplet design. By integrating AXI, CXS and CHI bus bridges, customers can achieve seamless system-level integration with industry-leading power efficiency and performance.

What would you say to a company considering joining the UCIe Consortium and supporting the chiplet ecosystem?

UCIe is the universal language of the chiplet ecosystem. It transforms the vision of “Lego-like” modularity into a technical reality through standardized die-to-die interfaces and compliance testing. For companies targeting the 2.5D/3D packaging space, we believe the Consortium offers the interoperability and scale needed to turn individual chiplets into high-performance systems.