Meet UCIe® Consortium Member: Socionext

By: Toshifumi Iwasaki, Chief Engineer, Global Leading Group, Socionext Inc.

UCIe® Consortium member Socionext recently shared details around its contribution to the development of the UCIe® (Universal Chiplet Interconnect Express®) specification, its roadmap for UCIe, and the value of joining the Consortium.

Can you share a brief introduction of Socionext?

Socionext is a global supplier of advanced SoC solutions, combining extensive experience in custom LSI development with deep expertise in imaging, networking, and high‑performance computing. Our focus is on highly optimized, application‑specific SoCs that deliver industry‑leading power efficiency and performance for markets such as data centers, automotive, broadcast, and industrial systems.

Leveraging our proven capabilities in high‑speed interfaces, advanced packaging technologies, and system‑level optimization, we provide customers with end‑to‑end semiconductor solutions — from architecture design through mass production.

What prompted Socionext to join the UCIe Consortium?

The semiconductor industry is rapidly shifting toward multi‑die architectures driven by performance scaling limits, cost efficiency, and the need for domain‑specific compute. UCIe provides the standardization required to enable interoperability across chiplets from different vendors, which is essential for the scalable growth of this new ecosystem.

For Socionext, joining the UCIe Consortium was a natural fit: our customers increasingly request flexible, modular SoC configurations that can be assembled from multiple die components. Being part of the Consortium allows us to help shape the evolution of this critical interconnect standard while ensuring our future SoC products align with global best practices.

What is the importance of a chiplet ecosystem to Socionext?

Our customers work in highly diverse application domains, each with unique performance, latency, and power requirements. A robust chiplet ecosystem enables us to tailor solutions more precisely — integrating compute, memory, accelerators, and I/O blocks that are best suited for each use case.

Chiplets reduce development time and overall system cost, while enabling architectural scalability far beyond monolithic SoCs. For Socionext, this means we can deliver higher‑value custom solutions with shorter time‑to‑market, while leveraging differentiated IP from ecosystem partners.

How does Socionext contribute or plan to contribute to the Consortium?

Socionext participates in the UCIe Consortium as a Contributor member company, with an interest in how UCIe‑based chiplet technologies may be applied to future SoC architectures. In particular, for automotive and other high‑reliability domains, Socionext is engaged in broader industry initiatives where advanced SoC architectures and system requirements are discussed. Through alignment with these ecosystem activities, we continue to explore the potential role of chiplet‑based approaches as the UCIe ecosystem evolves.

Moving forward, we plan to contribute to the evolution of the physical layer, testability standards, and best‑practice integration methodologies that will help accelerate UCIe adoption across mass‑production markets such as automotive and large‑scale compute.

Can you share some UCIe technology use cases that Socionext is bringing or will bring to the industry? Are there specific market segments that will benefit most from UCIe?

Socionext envisions UCIe playing a vital role in several domains:

• Data center acceleration: High‑bandwidth chiplet interconnects enable flexible integration of AI/ML accelerators, high‑speed networking modules, and memory expansion chiplets into a unified package optimized for power and performance.

• Automotive computing platforms: Software‑defined vehicles require heterogeneous compute elements—CPU, GPU, NPUs, and safety islands—working together with strict functional safety requirements. UCIe provides a scalable foundation for such platforms.

• High‑resolution imaging & video systems: By combining specialized ISP (Image Signal Processor) chiplets with domain‑specific compute units or memory-rich die, UCIe allows advanced imaging systems to scale more efficiently.

• Custom high‑performance industrial computing: Industrial systems often need long product lifetimes and flexible roadmaps. Chiplets allow us to mix technology nodes and extend product longevity while enhancing functionality.

Do you have any news or updates regarding your company’s roadmap for UCIe?

Socionext is actively evaluating UCIe‑based die‑to‑die technologies and their integration into future custom SoC platforms across data center and automotive markets. We are exploring multiple chiplet partitioning approaches—including domain‑specific accelerators, high‑speed I/O chiplets, and memory‑proximity compute blocks—and plan to introduce UCIe‑enabled custom SoC solutions as our ecosystem alignment progresses. We are also collaborating with packaging partners to evaluate 2.5D/3D/5.5D integration schemes that will complement UCIe‑based modular architectures.

What would you say to a company considering joining the UCIe Consortium and supporting the chiplet ecosystem?

The chiplet model is rapidly becoming a foundational shift in semiconductor design. Companies that adopt UCIe early will gain access to a global ecosystem that enables faster product development, broader interoperability, and reduced design risk. UCIe is more than just a physical interconnect — it is a collaborative framework that allows companies to innovate more freely, mixing best‑in‑class components regardless of vendor or process node. For any company seeking to build competitive SoCs in the coming decade, participation in the UCIe Consortium and contributing in its Work Groups is an excellent way to future‑proof their technology and accelerate their roadmap.