Promoting the Open Chiplet Ecosystem at Chiplet Summit 2026

The UCIe™ Consortium will be participating once again in this year’s Chiplet Summit at the Santa Clara Convention Center, February 17-19. The event serves as a place for the industry to gather and discuss innovations and the future of chiplet technology.

This year, the Consortium is expanding its presence in the event and showcasing the growing momentum behind UCIe by sponsoring the following activities:

• Keynote 4 - “Enabling an Open Chiplet Ecosystem at the Package Level” – Debendra Das Sharma, UCIe Consortium Chairman

  • Date and time: Wednesday, February 18, 12:00 pm PT

  • This session will cover the benefits of UCIe standard adoption as the de facto standard for die-to-die connectivity and the UCIe Specification 3.0.

• Pre-Con H - “Applying Die-to-Die Interfaces” Brian Rea, UCIe Consortium Marketing Working Group Co-Chair

  • Date and time: Tuesday, February 17, 2:10 pm PT

  • This tutorial will allow attendees to gain valuable insights into planning and building chiplet-based solutions aligned with UCIe specifications. Learn directly from the Co-Chairs of the electrical, protocol, and manageability/security working groups as they share practical advice, best practices, and address current challenges. The session will also feature an exciting interoperability case study presented by UCIe members Stephen Wong of Intel and Mayank Bhatnagar of Cadence. The tutorial will conclude with an interactive "Ask Me Anything" panel, providing a unique opportunity to engage with the experts.

• D-202: UCIe Version 3.0 (sponsored by UCIe) – Brian Rea, UCIe Consortium Marketing Working Group Co-Chair

  • Date and time: Thursday, February 19, 3:00 pm PT

  • This presentation will delve into real-world applications of the UCIe standard, focusing on the execution experiences of UCIe Consortium members. It will offer insight into how UCIe helps address integration challenges, optimize performance, and capitalize on UCIe 3.0’s capabilities for system-in-package designs across diverse markets.

UCIe Consortium can be found at Booth #211 and will include kiosks for member companies Intel and Alphawave Semi who will both perform demonstrations around their use cases for UCIe technology.

UCIe Consortium members are also presenting their UCIe solutions during the following sessions:

• Pre-conference tutorial: Introduction to Die-to-Die Interfaces (Sponsored by Alphawave Semi)  

  • Date and time: Tuesday, February 17, 8:30 am – 12:00 pm PT

  • Organizer and Moderator: Soni Kapoor, Alphawave Semi

• Keynote: Designing the Future Today: AI-Driven Multi-Die Design, Synopsys

  • Date and time: Wednesday, February 18, 10:10 am PT

  • Speaker: Abhijeet Chakraborty, VP Engineering at Synopsys

  • This keynote will explore how AI is revolutionizing multi-die design through advanced automation and will give a visionary perspective on the future of intelligent, automated multi-die design.

• Keynote: Engineering the Chiplet Era: Connectivity the Foundation of System-Level Design, Alphawave Semi

  • Date and time: Wednesday, February 18, 10:50 am PT

  • Speaker: Letizia Guiliano, VP of Product Marketing and Management at Alphawave Semi

  • This presentation explores high-performance, power-efficient connectivity as the critical enabler that determines scalability, interoperability and product viability.

• Keynote: Redefine 3D IC Performance for AI -- with AI, Siemens

  • Date and time: Wednesday, February 18, 11:30 am PT

  • Speaker: Juan Rey, Sr. Vice President, Segment Leader/General Manager at Siemens EDA

  • This keynote will examine the top barriers to 3D IC performance and reliability and outline the industry’s path toward a more open, holistic, AI-driven design flow.

• Keynote: Chiplets for Everyone, Cadence

  • Date and Time: Thursday, February 19, 10:10am

  • Speaker: David Glasco, VP of the Compute Solutions Group, Cadence

  • This keynote will discuss the current state of multi-die design, the evolving requirements for chiplets across data center, edge, and Physical AI applications, and the critical role of standardization and robust ecosystems in driving adoption.

• Keynote: Arm’s Open Chiplet Ecosystem for the Converged AI Datacenter, Arm

  • Date and Time: Thursday, February 19, 10:50 am PT

  • Speaker: Imran Yusuf, Director of Hardware Ecosystem at Arm

  • This keynote will highlight cloud providers and AI innovators already using chiplet-based integration to build more flexible and efficient infrastructure, demonstrating how an open chiplet ecosystem can scale innovation across all types of silicon and create a sustainable foundation for the next decade of AI and cloud growth.

• Keynote: Optimizing Cutting-Edge XPUs with Chiplets, Marvell

  • Date and time: Thursday, February 19, 12:00 pm PT

  • Speaker: Jim Rogers, SVP Custom Cloud Solutions at Marvell

  • This presentation will review the evolution of new memory and connectivity technologies in the form of chiplets – including 3D packaging, >30Tbps/mm D2D interconnect, custom SRAM, custom HBM, integrated power management, and integrated optics – that will dramatically reduce the power consumption and increase the performance of the next generation of XPUs.

Connect with UCIe experts at Chiplet Summit 2026!

We are looking forward to the great sessions and discussions at the Chiplet Summit. If you’re planning to attend the conference but have not yet registered, use this code to get $100 off your registration: CS26UCIE.  

We look forward to seeing you there!