UCIe 3.0 Specification: Redefining Chiplet Interconnects

UCIe Marketing
2 days ago
2 min read

The semiconductor industry is undergoing a seismic shift. Traditional monolithic chip designs cannot keep pace with skyrocketing demands in bandwidth, flexibility, and energy efficiency. Universal Chiplet Interconnect Express™ (UCIe™) is emerging to address this challenge by defining the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.

With the newly released UCIe 3.0 specification, the industry gains notable enhancements in bandwidth, efficiency, power saving, and manageability while maintaining full backward compatibility.

What’s Driving the Buzz? Press Coverage Highlights

UCIe 3.0 showcased impressive capabilities, including 48 GT/s and 64 GT/s data rates for both UCIe-S and UCIe-A packaging, runtime recalibration, extended 100 mm sideband reach, and advanced manageability features. The announcement not only piqued industry interest but also made waves across tech media. Below, we’ve shared a few highlights from leading technology publications about the announcement.

EETimes shared “the 3.0 version of its UCIe open standard, designed for high-speed, interoperable connectivity between chiplets in the same package.” The article also featured quotes from UCIe Consortium Chairman, Debendra Das Sharma.
ServeTheHome highlighted how UCIe 3.0 delivers “a big speed up for future generations of chiplets.”
The Next Platform featured the backward compatibility of the UCIe 3.0 specification, noting that “It’s also important as the reach of the standard expands. Its use in datacenter, HPC, and AI systems is well-documented, but it also will be universal.”

Key Enhancements in UCIe 3.0

Doubling the Data RatesUCIe 3.0 doubles data throughput, delivering 48 GT/s and 64 GT/s (up from 32 GT/s) for both 2D (UCIe-S) and 2.5D (UCIe-A) chiplet designs, meeting the ever-growing performance needs of high-demand applications such as AI, HPC, and advanced analytics.
Continuous Transmission SupportMaps ADC/DAC data directly via Raw Mode, enabling noise-sensitive designs such as DSPs and analog interfaces to synchronize without generating clocks that might interfere with noisy analog circuits.
Power Efficiency Enhancements Features like runtime TX-side recalibration and optimized L2 idle-state enable smarter power use by adjusting link timing dynamically and leveraging aggressive power gating to reduce energy consumption without sacrificing responsiveness.
Advanced Manageability for Complex Systems in Package (SiPs) Firmware management, low-latency signaling, and emergency controls empower safer, scalable, multi-chip systems.

Download the “UCIe 3.0 Specification: Driving Innovation for Efficient, Scalable, and Reliable Chiplet Integration” white paper HERE for a deeper dive into the specification.

Ready to Explore Further? Join the UCIe 3.0 Webinar!

On September 18 at 9 am PT, Dr. Debendra Das Sharma, UCIe Consortium Chairman, will delve into the new features in the UCIe 3.0 specification, including improvements to bandwidth density, power efficiency, enhanced manageability, and expanded design flexibility for scalable SiP architectures. Additionally, attendees will have a chance to participate in a live Q&A discussion immediately after the webinar to address questions from the presentation.