UCIe Foundries Q&A: Building the Future of Chiplet-Based Architectures
The semiconductor industry’s shift toward chiplet-based architectures is changing how companies approach system design, integration and innovation. As an open industry standard, the UCIe® Consortium is helping enable this transition by providing a standardized interconnect for chiplets within a package.
We are pleased to interview UCIe Consortium members on key issues shaping the evolving chiplet ecosystem. We recently asked Intel Foundry Services and Samsung Foundry about the trends driving chiplet adoption, the role of the broader ecosystem and how UCIe® can help address the cost, scalability, flexibility and connectivity challenges of increasingly complex semiconductor designs.
What recent technologies and market trends have driven the semiconductor industry's shift to chiplet-based architectures?
Intel: A big driver toward chiplet-based architectures is cost. Large monolithic die costs are high, driven by lower yield, and may not provide the best optimization or reuse opportunities. Using a mix of different technologies and/or foundry offerings can help optimize performance, power and area while enabling unique product requirements. Analog, digital and memory can now be mixed and matched using different advanced packaging techniques. For AI and HPC, integrating HBM in close proximity to XPU dies is critical, and chiplet integration provides an effective path to achieve it.
Samsung: The current semiconductor landscape is being redefined by the relentless demand for AI and high-performance computing, with hyperscalers driving a massive industry migration toward chiplet-based architectures. This shift marks a critical transition from traditional monolithic chip design to a system-based design philosophy. In this new paradigm, success is no longer determined by the performance of a single die, but by the ability to seamlessly integrate system-level design, high-speed memory and advanced packaging into a cohesive unit. Consequently, the adoption of the UCIe standard has become essential, providing the necessary interoperability to make these complex, multi-die systems viable.
Experience has shown that creating advanced chiplets requires a robust, collaborative ecosystem rather than isolated efforts. Samsung is uniquely positioned to facilitate this transition by offering a comprehensive, one-stop total solution that bridges the gap between design and delivery. By integrating leading-edge process technology, expert logic design services, memory integration know-how and advanced packaging, as well as a robust SAFE ecosystem of EDA, IP, and OSAT partners, this ecosystem enables our customers to realize the full potential of chiplet architectures.
As we see a significant uptick in customers adopting chiplet architectures, Samsung is actively involved in several ecosystem initiatives to create pre-designed chiplet platforms that can be customized for specific needs. In that spirit of offering new chiplet architectures more efficiently, the UCIe standards being developed and refined are accelerating chiplet adoption by standardizing component communication and providing designers with a consistent architectural foundation. Together, these capabilities maximize efficiency and help our customers remain competitive in a rapidly evolving market.
What role will foundries, OSATs, IP providers and system companies play in the chiplet ecosystem?
Intel: As a foundry, Intel can play a lead role in driving system technology co-optimization (STCO) for chiplet-based ecosystem products. Foundries can provide an end-to-end system foundry approach that can derive solutions optimized for product needs. Having the end-to-end system vision also drives new technology inventions, including Intel’s different EMIB technology variants.
Integrating chiplets, packages and boards together will also require the development of design methodologies and tools to ensure databases across multiple tools can be optimized in a judicious fashion.
How does UCIe help the industry address or overcome the scaling, cost, yield and flexibility limitations of monolithic SoC design?
Samsung: UCIe helps the industry overcome the inherent limitations of monolithic SoC design by shifting the paradigm from a single SoC model to a modular chiplet model. The primary advantage of this shift is the ability to optimize power, performance and area (PPA) at a granular level.
By leveraging a library of standardized chiplets, companies can mix and match components to create diverse product tiers or rapidly upgrade specific elements—such as swapping an older compute die for a newer 2nm version—without redesigning the entire system. This modularity significantly improves yield and reduces costs by utilizing smaller dies. Ultimately, this approach minimizes development risk and drastically accelerates time-to-market, enabling the industry to keep pace with the rapid evolution of AI.
Intel: UCIe standardizes chiplet interfaces and provides ease of integration. It gives products the flexibility to disaggregate what traditionally would have been a monolithic solution into chiplets. UCIe, along with different packaging solutions such as EMIB-T or Foveros, can help optimize each chiplet for the best fit, performance and cost.
UCIe standards also need to incorporate enhanced redundancy in the IP design to allow for higher yields at the high-layer-count, large-form-factor (HLFF) package system level.
How does UCIe enable innovation to address and improve connectivity in chiplet-based architectures?
Samsung: UCIe enables innovation in chiplet-based architectures by transforming connectivity from a complex, proprietary hurdle into a standardized interconnect design. The UCIe “plug-and-play” framework allows designers to integrate best-in-class components onto a single package. This ability to mix and match allows companies to innovate at the functional level rather than spending resources trying to map out and design a connectivity solution.
With UCIe as the connecting bridge between chiplets, the path to innovation becomes modular. Customers are no longer locked into a single design path; they can evolve their products by simply upgrading a specific chiplet without needing to redesign the rest of the system. This creates a future-proof architectural foundation where scalability is seamless, allowing our partners to respond to market shifts in real time while maximizing their investment.
How could UCIe transform semiconductor system architecture over the next decade?
Intel: UCIe helps lower overall system integration costs. The specification standardizes the chiplet interface and allows for flexible chiplet sourcing and integration. It enables chiplet reuse and provides a baseline for chiplet-based systems to begin optimizing and creating differentiated products.
For 2.5D and 3D chiplet designs looking to increase bandwidth, designers can lower their bump pitches without concern because this is already covered by the UCIe specification.
