UCIe™ Consortium to Keynote, Sponsor Inaugural Chiplet Summit
The UCIe™ Consortium is excited to announce its participation as an organizational sponsor in the inaugural Chiplet Summit – taking place January 24-26, 2023, in San Jose, CA.
The first annual Chiplet Summit will showcase the emerging chiplet market with an emphasis on semiconductor design, packaging, test, and integration in the chiplet era.
The event highlights the trends and individuals leading the adoption of this new technology, which impacts the design of a wide variety of extremely large integrated chips. The program will feature presentations, seminars, and panels on all aspects of chiplet-based development from experts that are using chiplets in designs for processors, communications chips, and Artificial Intelligence devices.
In addition to a dedicated UCIe Consortium exhibit, representatives from the organization will contribute to the inaugural program with the following sessions:
“UCIe™: An Open Interconnect Standard Between Chiplets Within a Package” Gerald Pasdast, UCIe Consortium Compliance Chair
Date and time: Tuesday, January 24, 8:30 am PT
This session details the industry initiative behind UCIe (Universal Chiplet Interconnect Express™) technology and takes a deep dive into the UCIe 1.0 specification, its key performance indicators, the factors impacting industry-wide adoption, technical characteristics, and more.
UCIe Table at the Chat with the Experts session – Gerald Pasdast, UCIe Consortium Compliance Chair with be on hand to answer attendee questions surrounding the new UCIe standard.
Date and time: Tuesday, January 24, 6 pm PT
“UCIe™ Consortium: Enabling an Open Chiplet Ecosystem at the Package Level” by Brian Rea, UCIe Consortium Marketing Chair
Date and time: Wednesday, January 25, 10:40 am PT
This session will provide a brief overview of the recently launched UCIe Consortium, including the motivations to align the industry around an open interconnect standard for chiplets and a summary of the organization’s inner workings.
UCIe Consortium members are also presenting on UCIe technology in the following sessions:
Pre-conference tutorial: Chiplet Basics
Date and time: Tuesday, January 24, 8:30 am – 12:00 pm PT
Organizer: Matt Ouellette, Director Silicon Product Planning, AMD
Moderator: Paul Franzon, Professor, North Carolina State University
Keynote: Leverage Agents to Boost Chiplet Design and Reliability
Date and time: Wednesday, January 25, 10:50 – 11:20 am PT
Speaker: Nitza Basoco, Vice President of Business Development, proteanTecs
Panel: Overcoming Chiplet Design Challenges – How Industry Can Help
Date and time: Wednesday, January 25, 2:00 – 3:00 pm PT
Organizer: Hugh Durdan, VP ASIC Business Development and Marketing, Marvell
Moderator: Jean Bozman, President, Cloud Architects Advisors
Patrick Soheili, Co-Founder, Eliyan
Rishi Chugh, VP Product Marketing, Cadence Design Systems
Nir Sever, Sr Director Business Development, proteanTecs
Hugh Durdan, VP ASIC Business Development and Marketing, Marvell
Technical talk: Performance and Reliability Monitoring of Die-to-Die Interfaces
Date and time: Thursday, January 26, 9:00 – 10:00 am PT
Speaker: Nir Sever, Sr Director Business Development, proteanTecs
Panel: How to Make Chiplets a Viable Market
Date and time: Thursday, January 26, 2:00 – 3:20 pm PT
Organizer and moderator: Ravi Agarwal, Technical Sourcing Manager, Meta
Durgesh Srivastava, Sr Director, NVIDIA
Clint Walker, VP Marketing, Alphawave IP Group
Mark Kuemerle, VP/CTO ASIC Business Unit, Marvell
Kevin Yee, Director IP Marketing, Samsung Semiconductor
Visit the Chiplet Summit 2023 website for additional event details and information on how to register.
We look forward to seeing you there!