Meet UCIe Consortium Member Synopsys
By Manuel Mota, Sr. Product Manager of Synopsys
UCIe Consortium member Synopsys shared details around its contribution to the development of the UCIe™ (Universal Chiplet Interconnect Express™) standard, use cases, and the benefits of becoming a UCIe Consortium member.
Can you share a brief introduction of Synopsys?
Synopsys technology is at the heart of innovations that are changing the way people work and play. Self-driving cars, machines that learn, lightning-fast communication across billions of devices in the datasphere: these breakthroughs are ushering in the era of Smart Everything―where devices are getting smarter and connected, and security is an integral part of the design. Powering this new era of innovation are high-performance silicon chips and exponentially growing amounts of software content. Synopsys is at the forefront of Smart Everything with the world’s most advanced technologies for chip design, verification, IP integration, software security and quality testing. We help our customers innovate everything from silicon to software so they can bring amazing new products to life.
What prompted Synopsys to join UCIe Consortium?
Synopsys has been developing high-quality IP for decades, actively participating in standards organizations to develop protocols for the most widely used interfaces. Our focus included die-to-die interfaces for multi-die systems with XSR and HBI/AIB IP which are in customer production today. We joined the UCIe Consortium to help with the development and adoption of the UCIe specification, which covers a complete protocol stack, promotes interoperability, and unifies a market that is otherwise fragmented. Since the inception of UCIe, we have put our entire focus on developing a high-quality UCIe solution that includes controller, PHY and verification IP, test, silicon lifecycle management, and emulation. UCIe converges on all aspects of die-to-die connectivity and multi-die systems from form factor to security to compliance, and more, while offering highly competitive technical capabilities. We are tracking more than 100 companies planning to deploy multi-die systems and have seen a significant increase in interest since UCIe initial release about a year ago. UCIe has taken hold in the industry and is quickly becoming the de-facto die-to-die interface. We are working with the ecosystem to move multi-die systems forward and accelerate the adoption of UCIe.
What is the importance of a chiplet ecosystem to Synopsys?
Multi-die system adoption is ramping up quickly, initially based on captive systems, but also progressing into a more open chiplet marketplace. We see multi-die systems as the next innovation wave in the semiconductor industry, offering designers to efficiently deliver innovative products with unprecedented functionality, reduce risk, accelerate time to market, and rapidly create new product variants with optimized system power and performance. Synopsys is well positioned to support the multi-die system ecosystem with our high-quality IP and IP subsystems, our integrated 3DIC die/package co-design and analysis platform, manufacturing optimization and reliability solutions.
How does Synopsys contribute/plan to contribute the Consortium?
Synopsys is a contributor member of UCIe Consortium, actively participating in workgroups to help evolve the UCIe standard. We are accelerating the adoption of UCIe across the industry by delivering a comprehensive UCIe IP solution, which has been adopted by multiple leading customers, and sharing our expertise for a better future with UCIe for multi-die systems.
Can you share some UCIe technology use cases that Synopsys is bringing/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?
Many markets can benefit from multi-die systems and UCIe. At first the shift from monolithic SoCs to multi-die systems started in the data center with large compute server and AI acceleration chips splitting into smaller dies either for performance scaling and easy creation of product variants or simply because dies were becoming too big for economic efficiency. We now see the shift expanding into other markets such as Automotive (ADAS), Networking, Consumer and Mobile, and more.
Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?
Synopsys is fully committed to delivering comprehensive UCIe IP solutions, supporting the most relevant process nodes from different foundries and the various protocols defined by UCIe. However we are going beyond just the IP by partnering with the ecosystem to offer solutions that enable seamless and very low latency bridges between common SoC fabrics in two dies, by providing comprehensive solutions for multi-die system reliability with built-in testing capabilities in the UCIe PHY, by leveraging our automotive expertise to develop automotive-grade IP, and by offering other solutions like mission mode link health monitoring for the UCIe interface, verification IP and hardware-assisted verification.
We recently announced our UCIe PHY IP on the TSMC N3E process has achieved first-pass silicon success, and our collaboration with Samsung to deliver a broad IP portfolio, that includes UCIe IP, across all advanced Samsung Foundry processes.
What would you say to a company considering joining UCIe and supporting the chiplet ecosystem?
The more we interact with customers and help them realize their UCIe-based multi-die system design success, the more convinced they are that UCIe is the lynchpin of multi-die system design. The more we continue to collaborate with other keystone companies in the ecosystem, the more convinced we are that UCIe is the enabler of multi-die systems. If a company is interested in riding the new innovation wave of multi-die systems in the SysMoore Era, they must join the UCIe Consortium to help define the future, which is clearly multi-die systems.