By Saman Sadr, President & CEO of Neuron IP
UCIe Consortium member Neuron IP recently shared its contribution to the development of the UCIeâ„¢ (Universal Chiplet Interconnect Expressâ„¢) standard, the importance of a chiplet ecosystem, and the benefits of becoming a UCIe Consortium member.
Can you share a brief introduction of Neuron IP?
Neuron IP is a Canadian company specializing in Advanced IC Design & Purpose-Built Silicon Interfaces. Our team has a proven track record of developing High-Speed Silicon Interface IPs with designs in 100’s of SOCs and shipped in 100’s of millions of product units. The markets we address are Disaggregation & Chiplets, PPA Differentiated solutions over standardized and proprietary connectively protocols - across AI/ML, HPC (Data Center & Cloud Computing), 5G/Wireless Base Station application verticals​ and continuing to service Tier 1 cliental worldwide.
What prompted Neuron IP to join UCIe Consortium?
A standardized chiplet silicon interface amounts to the most critical component of a chiplet and disaggregation ecosystem. Neuron IP is a company that is committed to creating a differentiation in this space and we are amongst the first companies starting the development of UCIe PHY & die-to-die adapters.
What is the importance of a chiplet ecosystem to Neuron IP?
The chiplet ecosystem is quite essential to Neuron IP’s mission as the developer of Interface and Smart Chiplets, as well as Silicon Interface IPs for chiplet integration, including PHYs & Adapters for both UCIe-A and UCIe-S.
How does Neuron IP contribute/plan to contribute to the Consortium?
The heritage and DNA of the Neuron IP team is based on more than two decades of developing high speed silicon interfaces, ranging from chip-to-chip interfaces to ultra long reach applications. Neuron IP brings a wealth of knowledge and experience in shipping state-of-the art silicon interfaces into 100’s of millions of advanced products across the spectrum of vertical applications. This knowledge and experience combined with innovation have been instrumental in creating PPA differentiated solutions particularly tackling power and latency of the end-to-end links in the chiplet ecosystem.
Can you share some UCIe technology use cases that Neuron IP is bringing/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?
Neuron IP is developing UCIe PHY & D2D adapter IPs for both advanced & standard packages in advanced technology nodes for chiplet products (2.5D and 3D advanced packaging) for various application verticals including Smart Chiplets, AI Empowered and Security Enabled SoC’s in the form of Known Good Die (KGD).
Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?
Neuron IP’s UCIe IP portfolio is designed for advanced technology nodes and the highest data rates, including 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S) as per the latest UCIe 1.1 Specification. Our team has been diligently developing compliant, PPA-differentiated architectures, with a feature-rich focus for rapid SoC chiplet integration by our customers. Inquiries for early deliverables are welcome.
What would you say to a company considering joining UCIe and supporting the chiplet ecosystem?
Advanced packaging will be an indisputable home for the new configurable SoC platforms, as chiplets and disaggregation has revolutionized silicon integration. The need for ‘standardized’ chiplet interfaces is an integral part of the evolution of silicon industry and pertaining to all fast-moving application verticals including HPC/Data Center, AI/ML, 5G, and Automotive.