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  • Brian Rea

UCIe™ Consortium Releases the UCIe 1.1 Specification at FMS 2023

By Brian Rea, UCIe Consortium Marketing Workgroup Chair


Last month, the UCIe™ (Universal Chiplet Interconnect Express™) Consortium participated in Flash Memory Summit (FMS) 2023 where we were pleased to announce the release of the UCIe 1.1 Specification and highlight the benefits of an open chiplet ecosystem.


During the conference, UCIe technology experts presented a deep dive into the UCIe Specification at the pre-conference seminar and discussed the manageability and software, protocol, and usage models for UCIe technology during the UCIe and Chiplets track. Additionally, Dr. Debendra Das Sharma, UCIe Consortium Chairman, delivered an invited talk to provide an overview of the UCIe Standard, the Consortium, and introduced the UCIe 1.1 Specification.


“FMS was a great opportunity to engage the memory and storage industry on the benefits of UCIe for building chiplet based solutions. Between our tutorial, invited talk, and exhibit booth, we engaged many thought leaders and engineers involved in the design and test of SOCs. We heard genuine intrigue about both the challenges and momentum we see in building a chiplet ecosystem, and we had great response to the progress we demonstrated through our 1.1 spec release.”
Brian Rea, UCIe Consortium Marketing Work Group Chair and Technology Initiative and Ecosystem Enablement Manager at Intel

“The one-hour invited talk, “UCIe™: Building an open ecosystem for chiplets for on-package innovations” had good attendance and lots of questions, and the session was covered by Forbes.
Dr. Debendra Das Sharma, UCIe Consortium Chairman and Intel Senior Fellow and co-GM Memory and I/O Technologies


Additionally, we had the opportunity to participate at SNIA’s Open Standards Pavilion, where we met with industry peers to introduce the UCIe Standard and highlight the valuable improvements that UCIe brings into the chiplet ecosystem.


“Chiplet architectures will have significant advantages over traditional monolithic designs to power the next generation AI workloads. The standardization of the die-to-die interface is crucial to optimizing performance, power, and cost of chiplets. This was abundantly clear at FMS with several technical presentations at FMS and discussions with UCIe partners and visitors at the UCIe booth.”
Archana Cheruliyil, Senior Product Marketing Manager, Alphawave Semi


We were excited to see that Tom Coughlin, FMS Program Chair, listed the UCIe 1.1 Specification announcement as a part of his Top 10 highlights from FMS. UCIe representatives will be participating in the Storage Developers Conference (SDC) 2023, OCP (Open Compute Project) Global Summit, and Supercomputing 2023 (SC’23) to discuss the benefits and opportunities for UCIe across the storage and high-performance computing industries. We hope to see you there!



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