Meet UCIe Consortium Member Cadence

By: Sue Hung Fung, Principal Product Marketing Manager, Cadence

Can you share a brief introduction of Cadence?

Cadence (Nasdaq: CDNS) is a pivotal leader in electronic systems design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial, and healthcare.

For nine years in a row, Cadence was listed on the Fortune Magazine 100 Best Companies to Work.

What prompted Cadence to join UCIe Consortium?

Cadence became a contributor-level member at the initial opening of the UCIe Consortium. Prior to joining the Consortium, Cadence demonstrated and proven capability in chiplet IP with their proprietary 40G die-to-die solution. Joining the UCIe Consortium gives Cadence the opportunity to participate in the advancement of the open chiplet ecosystem. Our representative’s expertise, knowledge, and familiarity with chiplets, PCIe®, CXL™, and streaming protocols allow Cadence to rapidly design and develop UCIe technology. The rapid scaling of silicon-proven functionality and architecture improves customer time to market and reduces developmental risk in the design implementation of UCIe.

What is the importance of a chiplet ecosystem to Cadence?

Cadence enables die-to-die IP designs and solutions. Engagement in the open ecosystem provides a path forward to producing reusable chiplet IP for interoperability with other chiplets. Interoperability in the chiplet ecosystem and provision of a fully integrated PHY and controller UCIe platform solution allows customers a reduction of product development time to focus on their own design and custom needs.

Customers can lower their overall portfolio costs and accelerate their product development cycles by reusing chiplet designs already established on their preference of process nodes. By reusing designs on a variety of established process nodes, on-package integration of those designs can be used to lower overall portfolio costs. Cadence’s engineering teams are well equipped to rapidly create a variant of the UCIe PHY and Controller aimed at lowering system power, increasing bandwidth and throughput, and reducing overall die-to-die link latency.

How does Cadence contribute/plan to contribute to the Consortium?

Cadence currently engages in the Electrical, Form Factor & Compliance, Manageability & Security, Protocol, Systems & Software, and Marketing Working Groups to help steer and develop the new chiplet open standard. Cadence has a broad portfolio of automotive IP solutions and is currently engaging in the Automotive Working Group. Cadence’s extensive experience and history in the design and development process of die-to-die solutions will efficiently impact UCIe’s future course of action to create a strong infrastructure around these specific Working Group categories within the UCIe standard.

Cadence currently has PHY and controller IP solutions in PCIe and CXL. Cadence’s proprietary chiplet controller solutions already offer streaming, CXS.B, and AXI protocols on chiplet interfaces. Building upon prior experience, the extensive background and expertise in these current IP and chiplet solutions provide a knowledge base to contribute and improve upon within the Consortium.

Can you share some UCIe technology use cases that Cadence is bringing/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?

The automotive segment is a strong focus where Cadence is proud to bring expertise and improvement to the open standard. Cadence has a broad portfolio of automotive controller and PHY IP solutions. The UCIe Protocol Working Group has addressed mainband data integrity protection as a part of ECN1 in the next UCIe Rev 1.1. By adding CRC and retry for a UCIe streaming controller, automotive applications can lean heavily on CRC as the primary safety mechanism for the mainband data path. In addition to this, Cadence is providing a proprietary proposal to ensure sideband message protection and integrity for automotive safety.

Cadence’s EDA tools for advanced and standard package designs allow customers to sign off with a full integration of multi-chiplet design. With top-level planning, 3D place and route, packaging, and thermal analysis, Cadence’s tools provide designers with full capability to improve PPA, increase performance, and close timing.

Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?

Cadence is currently offering UCIe on multiple foundries and nodes and has taped out an advanced-package UCIe solution on 3nm. We are working with multiple customers towards the expansion of UCIe on additional technology process nodes, at a variety of foundries, and across both standard and advanced package options.

Cadence is also working with multiple customers to focus on automotive applications with UCIe. With a vast track record of automotive products already available, the addition of UCIe to the portfolio will enable customers to scale their products for robust automotive applications in chiplets.

What would you say to a company considering joining UCIe and supporting the chiplet ecosystem?

UCIe is the open standard of the future of interoperable chiplet communication. Die link communication via UCIe’s standard will advance an open ecosystem where chiplets from different vendors can be designed for interoperability. With die sizes reaching their maximum reticle limits, the need for disaggregation of SoCs will drive future-generation designs to move toward chiplet solutions. Smaller die will result in higher manufacturing yields and lower costs. Chiplets will allow flexibility on the process nodes of choice (heterogeneous platforms), where the process technologies of preference can be integrated on-package. Join the UCIe Consortium to help advance chiplet integration and support interoperability within the ecosystem.