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  • UCIe Marketing

Meet UCIe Consortium Member Ayar Labs

By Lakshmikant (LK) Bhupathi, Vice President of Products, Strategy and Ecosystem, Ayar Labs

UCIe Consortium member Ayar Labs provided an update on its contribution to the development on the UCIe™ (Universal Chiplet Interconnect Express™) standard, optics in chip-to-chip interconnects, and the variety of applications for UCIe technology.

Brief introduction of Ayar Labs:

Ayar Labs was founded in 2015 and is funded by GlobalFoundries, NVIDIA, Intel, HPE, Lockheed Martin, and leading venture investors. We are using light to fundamentally upgrade traditional compute architectures by delivering power efficiency and enhancing the performance curves. Our approach uses silicon photonics techniques to replace traditional electrical-based I/O with a high-speed, highly efficient, chiplet-based optical interconnect solution that is powered by a multi-wavelength light source. Our goal is to bring optical technology as close to the compute chip as fast as possible. By directly converting electrical interfaces into optical links in the package, our optical I/O chiplet-based solution enables the next design breakthrough for multi-terabit per second connections required for next-generation AI infrastructure, disaggregated data centers, 6G deployments, phased array sensory systems, and more.

What prompted Ayar Labs to join the UCIe Consortium?

The UCIe Consortium plays a central role in the success of our optical I/O solution by providing a highly efficient and standard chiplet interface specification that is a perfect fit for our optical I/O chiplet. There is a lot of synergy between what we hope to achieve with our technology and what the consortium is proposing around chiplet interface standards. The standardized interface UCIe employs — through which compute chips and other SOC die made by our customers can communicate with our chiplet — is essential to the wide-scale adoption of in-package optical I/O.

For us, the standard ensures that UCIe-compatible interfaces are built to be compatible with optical links we enable, and having a standardized interface for die-to-die interconnects enables us to offer a solution that can easily plug and play with multiple customer chips. Perhaps, most importantly, the consortium’s efforts go hand in hand with our goal of establishing a robust ecosystem around standardized chiplet adoption.

What is the importance of a chiplet ecosystem to Ayar Labs?

At Ayar Labs our solution is primarily offered in the form of a chiplet. Our optical I/O technology uses a photonics process while most compute and SOC designs are implemented in advanced CMOS process nodes. Use of chiplets is essential to realize the benefits of our technology.

Historically speaking, multiple dies inside a package were relatively uncommon, but the chiplet approach is gaining a lot of traction. Now the infrastructure — packaging houses, OSATs, and test methodologies, for example — must come together for a chiplet marketplace to thrive.

In the same way that organizations buy chips from different vendors and place them on printed circuit boards, we will soon see them assembling package-level solutions by sourcing chiplets from different vendors. As such, we need a standard way to connect, build, and test those chiplets. UCIe is an integral part of the development of that ecosystem, which needs to come together for chiplets to have a truly plug-and-play multi-vendor marketplace.

How does Ayar Labs contribute/plan to contribute to the consortium?

The UCIe standard is key to the future of optical interconnects at scale, which is why we are excited to contribute to the consortium. We participate in many of the technical meetings that discuss the specifications. Consider this: today’s large compute systems typically use an architecture where compute and memory resources are tightly coupled to maximize performance. Components such as CPUs, GPUs, and memory must be placed closely together when connected electrically via copper interconnects. This hardware density results in cooling and energy issues, while persistent bandwidth bottlenecks limit inter-processor and memory performance. These issues are exacerbated in compute-intensive applications like HPC, AI, and data analytics.

We are focused on bringing optical I/O into the data center to replace copper interconnect for the rack-level links to solve bandwidth density and scaling problems. And in doing so, the emphasis of our contributions to the consortium will come in developing standardized solutions that incorporate optics into chip-to-chip interconnects that can meet the demands of these HPC and AI system architectures.

Can you share some UCIe technology use cases that Ayar Labs brings/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?

UCIe, like optical I/O, is not beholden to a specific market segment, so it is a net positive for any industry that benefits from a modular in-package chiplet infrastructure. Any application that needs high-throughput, low-latency, and power-efficient interconnect will benefit. HPC and AI are prime market segments that are growing and changing rapidly. As a result, these segments will likely benefit most from the UCIe standard because they seek solutions that can help alleviate performance bottlenecks, enable disaggregated systems, and rapidly build and modify design architectures based on their needs. UCIe and optical I/O will enable AI/ML architects to keep their system designs on pace with the rapid growth of model sizes. Other markets that will benefit from UCIe standardization include aerospace and defense, telecommunications, and autonomous driving, to name a few,

Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?

We are very excited to see the UCIe standard evolve, and we are eager to continue working with the consortium to ensure our future products align with the standard. We recently demonstrated an optical I/O solution that uses an Advanced Interface Bus (AIB), allowing for a straightforward interface adjustment to UCIe. We started using these wide parallel interfaces before the adoption of the UCIe standard. UCIe is an enhancement of the AIB interface, and existing optical I/O chiplets can easily be modified or transitioned to a UCIe interface-based solution. The broad industry support UCIe has already achieved is promising as we scale our solutions for many years to come.

What would you say to a company considering joining UCIe and supporting the chiplet ecosystem?

The consortium has a lot of momentum in terms of the number of companies that are a part of the standardization effort and the number of companies developing products around the UCIe interface. We would like to see everyone come together around one standard and encourage everyone to contribute to the standardization effort or participate in developing technologies and solutions around UCIe.

Ultimately, organizations risk potentially missing out if they do not join and support the consortium. In talking with our customers, their efforts are centered mainly around UCIe as the interface of choice for our chiplet. Simply put, whether your company is developing chiplets or plans to use them, joining the UCIe Consortium is the right decision.


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