Meet UCIe™ Consortium Member Alphawave Semi
By Letizia Giuliano, VP of IP Product Marketing and Management at Alphawave Semi
UCIe Consortium member Alphawave Semi recently shared details around its contribution to the development of the UCIe™ (Universal Chiplet Interconnect Express™) standard, their roadmap for UCIe, and the benefits of becoming a UCIe Consortium member.
Can you share a brief introduction of Alphawave Semi?
Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need – enabling data to travel faster, more reliably, and with higher performance at lower power. Our mission is to accelerate the critical data infrastructure at the heart of our digital world. We are a vertically integrated semiconductor company, and our IPs, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, high performance computing, networking, AI, 5G, autonomous vehicles, and storage.
Additionally, Alphawave Semi's chiplet-based design approach has enabled our customers to create complex systems-on-a-chip (SoCs) that offer high performance, low power, and reduced costs. By leveraging chiplet-based design, Alphawave Semi technology can quickly enable new Systems in Package (SiP) by integrating multiple pre-designed chiplets into a single chip, thereby reducing design time and costs. To find out more about Alphawave Semi, visit: awavesemi.com.
What prompted Alphawave Semi to join the UCIe Consortium?
Today, most chiplet-based logic products are based on closed interfaces and integrate die from a single company, thereby creating silos of inter-company technical specifications, workflows, and business requirements. We at Alphawave Semi believe that it is an obvious choice for the industry to demand more chiplet integration to accelerate its adoption. Standardization of the die-to-die interface is one of the most important efforts for building the universal chiplet ecosystem. Alphawave Semi is proud to be a contributing member of the UCIe Consortium, applying our decades of experience in delivering custom silicon and our industry leading connectivity focused IP catalog to create a robust ecosystem of chiplet interoperability.
What is the importance of a chiplet ecosystem to Alphawave Semi?
The chiplet-based design approach offers a flexible and scalable method for designing and developing the next generation of data center products. It also empowers system architects with new tools to revolutionize the distribution of functions. Furthermore, intelligent integration of different chiplets allows for cost and time-to-market reductions, eliminating the need to replace an entire monolithic design simultaneously. By transforming our chiplet customized silicon into components, we can preassemble them in a SiP. We firmly believe that SiP technology represents the motherboard of tomorrow.
Standardizing the interconnect across multiple dies has the potential to democratize this intricate technology. It can expedite time-to-market and foster innovation on a larger scale than ever before, especially as we stand at the threshold of the AI era. Leveraging existing and established protocol interfaces such as PCIe, and CXL means we can avoid reinventing the wheel and focus on delivering a high-bandwidth-density interface that is universally applicable to all implementers.
How does Alphawave Semi contribute/plan to contribute to the Consortium?
Our design methodology for complex high-speed interface circuits is based on a unique and innovative approach. This approach has yielded circuits that are faster, smaller, and more power-efficient.
One of our notable strengths lies in our proficiency in designing high-speed interface IP, which plays a crucial role in the advancement of die-to-die interconnect for future generations. Our team actively contributes to the Electrical, Protocol, Form-Factor, and Compliance groups to ensure the development of effective, efficient, and interoperable standards. By doing so, we aim to foster a thriving ecosystem that benefits both users and designers alike.
Can you share some UCIe technology use cases that Alphawave Semi is bringing/will bring to the industry? Are there any specific market segments that will benefit most from UCIe?
There are two specific factors that come to mind: the move to a chiplet-based design paradigm and our team's unparalleled expertise in high-speed interface analog IP, which forms the foundation of our solutions.
In response to the industry's evolving needs, we have gone down the chiplet path, leveraging our silicon proven building blocks and custom silicon expertise. Like a motherboard, our custom silicon expertise allows us to use prebuilt chiplets and seamlessly integrate them to deliver high-bandwidth and power-efficient connectivity, including optical chiplets for traditional cabling applications.
The chiplet design approach enables the reuse of silicon IPs and older technologies, which can significantly reduce the risk and time-to-market and therefore total cost involved in new product development.
By using pre-designed and pre-verified chiplets, chip designers can accelerate the design process and reduce the risk of chip failure.
One of our key strengths is our expertise in designing high-speed interface IP. Our team of experienced engineers has developed a suite of analog IP products with superior performance and low power consumption.
Do you have any news or updates you want to share regarding your company’s roadmap for UCIe?
We are delighted to announce successful tapeouts on TSMC’s most advanced 3nm process including UCIe PHY IPs. This marks a significant accomplishment for Alphawave Semi and the UCIe specification as it paves the way for a new generation of chiplet-enabled silicon platforms, tailored for hyperscaler and data infrastructure customers. This achievement is particularly noteworthy as we have achieved full support for both UCIe-Advanced and UCIe-Standard (up to 24Gbps), making it an industry first.
Alphawave Semi plays a pivotal role in fostering an open ecosystem across the entire protocol stack. Our AresCORE D2D electrical PHY leverages optimization techniques to deliver high bandwidth density, low power consumption, and minimal latency. It is compatible with all package types. Additionally, we offer a die-to-die adapter that facilitates management control and parameter negotiations, essential for achieving multi-vendor chiplet interoperability. Furthermore, our controllers for streaming protocol (GammaCORE) or connectivity technologies such as PCIe® (PiCORE) and CXL™ (KappaCORE) are ready for seamless integration into customer chiplet designs.
What would you say to a company considering joining the UCIe Consortium and supporting the chiplet ecosystem?
The chiplet ecosystem has the potential to revolutionize the semiconductor industry. Chiplets offer opportunities for faster time-to-market, increased performance, reduced costs, and improved flexibility in designing complex integrated circuits. By joining UCIe Consortium, a company can unlock new avenues for growth, enabling modular design, improved scalability, and enhanced customization. By participating in the Consortium, a company can contribute to the development of industry standards and best practices for chiplet integration. This involvement can help shape the future of chiplet technology, ensuring interoperability, compatibility, and seamless integration among different chiplet designs. Active engagement in standardization efforts can enhance your company's reputation as an industry leader, like Alphawave Semi.