Specifications
The UCIe™ Specifications are an open industry standard developed to establish a ubiquitous interconnect at the package level and covers the die-to-die I/O physical layer, Die-to-Die protocols, and software stack which leverage the well-established PCI Express® (PCIe®) and Compute Express Link™ (CXL™) industry standards. The specifications are available by request below.
UCIe 1.0 Specification
​The UCIe specification details the complete standardized Die-to-Die interconnect with physical layer, protocol stack, software model, and compliance testing that will enable end users to easily mix and match chiplet components from a multi-vendor ecosystem for System-on-Chip (SoC) construction, including customized SoC. ​
In-Standard & Advanced Package Benefits
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Enables construction of SoCs that exceed maximum reticle size
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Reduces time-to-solution
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Lowers portfolio cost (product & project)
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Enables a customizable, standard-based product for specific use cases
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Scales innovation (manufacturing and process locked IPs)
UCIe 1.1 Specification
The UCIe 1.1 Specification delivers valuable improvements in the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. Additional enhancements are included for automotive usages – such as predictive failure analysis and health monitoring – and enabling lower-cost packaging implementations. The specification also details architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The UCIe 1.1 Specification is fully backward compatible with the UCIe 1.0 Specification.
Highlights of the UCIe 1.1 Specification:
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Architectural Specification Enhancements enable compliance testing
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Supports simultaneous multiprotocol with full link layer functionality for streaming protocols
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Includes runtime health monitoring and repair for automotive and high-reliability applications
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New bump maps result in lower cost packaging